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2:23 p.m.

Ok, there are some small diodes on the input path after the resistor. But still, the main clamp are the actual drive transistors AFAICT.

The small diodes are standard (from what I've seen). Usually the path is: ESD main protections (GT mos or similar) - resistor - "small diodes" - core of the circuit

If properly designed output drivers can indeed also be used as ESD protection. This is using the so-called snap-back behavior. I believe this should explain something. I used 0.18um TSMC when @imec and both IO NMOS and PMOS were designed to have that capability. (edited)

Explain the snapback phenomenon in NMOS devices - Siliconvlsi

The snapback phenomenon in NMOS devices is an important aspect in understanding their behavior and reliability.

Brunny

The small diodes are standard (from what I've seen). Usually the path is: ESD main protections (GT mos or similar) - resistor - "small diodes" - core of the circuit

It is known to me as secondary protection and the purpose is to get some extra voltage drop over the resistance during an ESD event to protect the connected gates. The diode also has a capacitance so the R-C acts as a low-pass filter on the input though so high frequency stuff typically needs IO with custom ESD protection. (edited)

Tx both, yeah I knew the secondary protection thing. But never heard of snapback.

Here are the ESD guidelines from the PDK: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_14_4.html It seems like the snapback behavior is indeed used for ESD protection.

There are ESD implants available specifically only for thick oxide area's sd-diffusion.

6:27 p.m.

There's also a trick were you employ something like a gate-triggered TRIAC that's constructed to bascially experience a safe and depending on details maybe or maybe-not power-cycle-requiring latchup to clamp the ESD voltage below what a passive diodes-to-PDN-rails arrangement could do, to be useful whenever thin-oxide devices are used to interact with pads. An example that comes to mind would be e.g. DDR3 which is nominally 1.5V and fairly intense on the IO power draw due to combination of frequency, receive-side-termination, and ofc sheer wire count.